Intel decided to cut the waiting, and give us some new Larrabee details to chew on, until an official and complete presentation will become available. The chipmaker promises to deliver in Larrabee improved performance, based on a new technology that will include at least ten x86 CPU cores onto a single chip, instead of the traditional GPUs.

We know that the company is planning an official product launch somewhere in 2009 or 2010, but there are still a lot of details that we still don’t know about Larrabee. However, there is something we can say for sure: Larrabee will put rivals Intel in a direct competition with ATI and NVIDIA on the PC gaming market.

But Larrabee is not all about the future of gaming PC, which will be just one of its major assets. In addition to that, Intel engineers have explained that the multi-core model will be capable of executing a wide variety of tasks, and process almost a trillion instructions per second.

Intel’s upcoming Larrabee architecture relies on visual computing, and compared to mainstream graphics that offer rigid architecture and are inefficient for non-graphics computing, Larrabee comes with programmable architecture, high definition audio and video processing, and combines with model based computing.

With Larrabee, Intel is entering a new era of parallel computing, offering developers means of creating graphics –intensive applications. Furthermore, Intel supports the industry-standard application programming interfaces Direct X and Open CL. As Intel’s Visual Computing Group senior engineer Larry Seller pointed out in a brief presentation, Larrabee doesn’t require a special API, and existing games will be able to run on Larrabee products.

According to Seller, the graphics and general data parallel application market need an architecture capable of combining the programming abilities of a CPU, the full capabilities of a CPU together with the parallelism in graphics processors, which makes Larrabee a practical solution that breaks the limitations of current graphics processors.

“The thing we need is an architecture that combines the full programmability of the CPU with the kinds of parallelism and other special capabilities of graphics processors,” said Seller. “And that architecture is Larrabee.”

The chipmaker described Larrabee as the industry’s first many-core x86 Intel architecture. Larrabee is expected to respond to efforts of creating optimized computers capable of responding to continuously growing demands.

The Larrabee architecture is based on the dual-issue Intel Pentium processor, using a short execution pipeline, offering a vector processing unit, multi-threading, 64-bit extensions and sophisticated pre-fetching. Furthermore, the architecture uses a 1024 bits-wide and bi-directional ring network (512 bits in each direction) for fast communication between cores.

It still remains unclear what Larrabee can do in terms of performance, as Intel chose to keep silent for now, but there’s no doubt about it, Intel is preparing something bigger than what we’ve seen so far. More details about Larrabee are expected to be unveiled during an industry conference scheduled to take place in San Francisco next week.

The chip could give the market a "significant boost," according to analyst John Peddie.

Additional details of the Larrabee architecture discussed in this paper include:

• The Larrabee architecture has a pipeline derived from the dual-issue Intel Pentium® processor, which uses a short execution pipeline with a fully coherent cache structure. The Larrabee architecture provides significant modern enhancements such as a wide vector processing unit (VPU), multi-threading, 64-bit extensions and sophisticated pre-fetching. This will enable a massive increase in available computational power combined with the familiarity and ease of programming of the Intel architecture.
• Larrabee also includes a select few fixed function logic blocks to support graphics and other applications. These units are carefully chosen to balance strong performance per watt, yet contribute to the flexibility and programmability of the architecture.
• A coherent on-die 2nd level cache allows efficient inter-processor communication and high-bandwidth local data to be access by CPU cores, making the writing of software programs simpler.
• The Larrabee native programming model supports a variety of highly parallel applications, including those that use irregular data structures. This enables development of graphics APIs, rapid innovation of new graphics algorithms, and true general purpose computation on the graphics processor with established PC software development tools.
• Larrabee features task scheduling which is performed entirely with software, rather than in fixed function logic. Therefore rendering pipelines and other complex software systems can adjust their resource scheduling based each workload's unique computing demand.
• The Larrabee architecture supports four execution threads per core with separate register sets per thread. This allows the use of a simple efficient in-order pipeline, but retains many of the latency-hiding benefits of more complex out-of-order pipelines when running highly parallel applications.
• The Larrabee architecture uses a 1024 bits-wide, bi-directional ring network (i.e., 512 bits in each direction) to allow agents to communicate with each other in low latency manner resulting in super fast communication between cores.
• The Larrabee architecture fully supports IEEE standards for single and double precision floating-point arithmetic. Support for these standards is a pre-requisite for many types of tasks including financial applications.

The paper's reference details: Seiler, L., Carmean D., Sprangle, E., Forsyth, T., Abrash, M., Dubey, P., Junkins, S., Lake, A., Sugerman, J., Cavin, R., Espasa, R., Grochowski, E., Juan, T., Hanrahan, P., 2008. "Larrabee: A Many-Core x86 Architecture for Visual Computing," ACM Transactions on Graphics, 27, 3, 2008.